1. Field of the Invention
The present invention relates to charged-beam exposure such as electron- or ion-beam exposure used in semiconductor device fabrication and more particularly, to a charged-beam exposure mask having different cell apertures each of which typically corresponds to unit repetitive patterns of an integrated circuit (IC) chip, and a charged-beam exposure method using the exposure mask.
2. Description of the Prior Art
In recent years, the need for high throughput has been becoming stronger and stronger in semiconductor device fabrication processes with the progressing integration scale and increasing packing density in ICs. It is needless to say that this need is applied to lithography processes using an electron beam, i.e., electron beam lithography.
To cope with the need for higher throughput, an improved method termed the "cell projection method" has been developed in electron-beam lithography. With this "cell projection method", typically, an exposure mask has different cell apertures, each of which corresponds to unit repetitive patterns of an IC chip, in addition to a shaping aperture for forming a variable-shaping aperture. On use, an electron beam is repetitively irradiated to the individual cell apertures or the shaping aperture for each IC chip.
FIG. 1 shows an example of the conventional exposure masks designed for the cell projection method. In FIG. 1, a plurality of apertures 102a, 102b, and 102c are regularly formed in a substrate 101 of a conventional exposure mask 100.
The shaping aperture 102a, which is rectangular and serves to form a variable-shaped electron beam, is located in the central area of the substrate 101. The cell apertures 102b, each of which corresponds to unit repetitive patterns of an IC chip, are located in the peripheral area of the substrate 101. The cell apertures 102c, each of which corresponds to unit repetitive patterns of the same IC chip, are located in an intermediate area of the substrate 101. The geometry of these cell apertures 102b and 102c is determined according to the designed layout (or exposure) data of the IC chip.
The selection of the apertures 102a, 102b, and 102c is carried out by deflection of an electron beam. Specifically, as shown in FIG. 2, a rectangular-shaped electron beam 121 is irradiated toward the conventional exposure mask 100. The beam 121 has been shaped into a rectangle by a beam-shaping mask (not shown) located between an electron source and the mask 100.
The electron beam 121 is deflected by a beam deflector (not shown) located between the beam-shaping mask and the exposure mask 100 so as to be irradiated to one of the apertures 102a, 102b, and 102c, thereby selecting the aperture 102a, 102b, or 102c. The beam 121 having passed through the selected aperture 102a, 102b, or 102c is projected on an area of an electron-beam resist layer on a semiconductor wafer, thereby transferring the patterns corresponding to the apertures 102a, 102b, and 102c onto the resist layer.
The layout or arrangement of the apertures 102a, 102b, and 102c is optionally determined according to an intention of a mask designer.
With the conventional exposure mask 100 shown in FIG. 1, when the electron beam 121 is irradiated to the shaping aperture 102a located in the central area of the mask 100, no deflection is necessary for the beam 121, because the axis of the beam 121 is designed to be aligned with the center of the mask 100.
However, when the electron beam 121 is irradiated to any one of the cell apertures 102b and 102c located in the peripheral and intermediate areas of the mask 100, the beam 121 needs to be deflected by an angle .theta. with the use of the beam deflector. It is clear that the value of the angle .theta. for the cell apertures 102b in the peripheral area is greater than that for the cell apertures 102c in the intermediate area.
The deflection distortion and aberration of the beam 121 increases with the increasing amount of the beam deflection, i.e., the deflection angle .theta.. Therefore, obtainable pattern-placement accuracy on a semiconductor wafer will degrade proportional to the deflection angle .theta.. This means that some problems will occur due to the degradation in pattern-placement accuracy when one of the apertures 102b in the peripheral area of the mask 100 is selected.
To solve the above problems due to the degradation in pattern-placement accuracy, conventionally, various approaches have been made for the purpose of decreasing the deflection distortion and aberration of the electron beam 121.
For example, an improved electron beam exposure system is disclosed in the Japanese Non-Examined Patent Publication No. 7-201701 published in August 1995. With this system, a driving voltage applied across a pair of opposing electrodes forming a sub beam deflector is increased by a specific amount according to the deflection amount of an electron beam caused by a main deflector. At the same time, another driving voltage applied across another pair of opposing electrodes forming the sub beam deflector is decreased by the same specific amount. Thus, the aberration of the electron beam is compensated.
Further, an improved deflection compensation method of an electron-beam exposure system is disclosed in the Japanese Non-Examined Patent Publication No. 7-142321 published in June 1995. In this method, the deflection amount of an electron beam is measured when a mark formed at a specific location on a semiconductor wafer is detected in a first step. Next, the measured deflection amount is set as compensation data for the electron beam in a second step. A time period until the measured deflection amount will reach the maximum tolerance limit is predicted based on the changing rate of the measured deflection amount in a third step. The first, second, and third steps are directed to be performed for a next measurement at the time when the predicted time period will be passed in a fourth step.
With the conventional techniques disclosed in the Japanese Non-Examined Patent Publication Nos. 7-201701 and 7-142321, however, there are the following problems.
Because these conventional techniques necessitate the structural change of the electron-optical system for deflecting an electron beam, the resultant electron exposure system will have a complicated structure. Also, they are unable to completely eliminate the above-described problems due to the degradation in pattern placement accuracy.
Especially, in recent years, miniaturization of the semiconductor devices or ICs has been progressing more and more and therefore, the required pattern-placement accuracy in electron beam lithography has been becoming severer and severer. From this point of view, it is difficult for the conventional techniques disclosed in the Japanese Non-Examined Patent Publication Nos. 7-201701 and 7-142321 to realize the satisfactory pattern-placement accuracy.